Four-quadrant current multiplier and its application as a phase-detector

Author

Abou El-Atta, M.A. ; Abou El-Ela, M.A. ; El Said, M.K.

Author_Institution

Electron. & Commun. Dept., Ain Shams Univ., Cairo, Egypt

fYear

2002

fDate

2002

Firstpage

502

Lastpage

508

Abstract

A four-quadrant current multiplier circuit is presented. It is based on the current-mode approach and the square-law characteristics of a MOS transistor in saturation. The analog multiplier is realized by using two squarer circuits biased by a common biasing network. Simulation was carried out using Pspice 7.1, with SCNA parameters obtained through MOSIS. Simulation results show that, for a power supply of ±3 V, the multiplier has a -3 dB bandwidth of 10.7 MHz. The total harmonic distortion is less than 0.14% with input ranges up to ±97.5 μA. The multiplier circuit is used as a phase-detector. The transfer characteristics of the detector is obtained and the piecewise linearization is performed.

Keywords

MOSFET; SPICE; analogue multipliers; circuit simulation; multiplying circuits; phase detectors; piecewise linear techniques; MOS transistor; MOSIS; Pspice 7.1; SCNA parameters; analog multiplier; bandwidth; biasing network; four-quadrant current multiplier; phase-detector; piecewise linearization; simulation results; square-law characteristics; squarer circuits; total harmonic distortion; transfer characteristics; Analog computers; Bandwidth; Circuit analysis; Circuit simulation; Circuit synthesis; Dynamic range; Linearity; MOSFET circuits; Phase modulation; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Science Conference, 2002. (NRSC 2002). Proceedings of the Nineteenth National

Print_ISBN

977-5031-72-9

Type

conf

DOI

10.1109/NRSC.2002.1022660

Filename

1022660