A topology-based multi-way circuit partition for ASIC prototyping

Author

Choi, Yhonkyong ; Jeong, Young Suk ; Rim, Chong S.

Author_Institution

Dept. of Comput. Sci., Sogang Univ., Seoul, South Korea

Volume

1

fYear

1996

fDate

18-21 Aug 1996

Firstpage

357

Abstract

In this paper, a new circuit partition problem is described for programmable circuit boards which consists of FPGAs and interconnect components, and whose routing topology among chips are predetermined. Since the new partition problem has some constraints that is difficult to be satisfied by the previous partition method, an efficient simulated annealing based partition method enhanced by tree clustering techniques is described. Experimental results for several circuits show that the method gives very good solution

Keywords

application specific integrated circuits; field programmable gate arrays; integrated circuit layout; logic partitioning; network topology; simulated annealing; trees (mathematics); ASIC prototyping; FPGA chip; interconnect; multi-way circuit partition; programmable circuit board; routing topology; simulated annealing; tree clustering; Application specific integrated circuits; Circuit simulation; Circuit topology; Field programmable gate arrays; Integrated circuit interconnections; Partitioning algorithms; Programmable circuits; Prototypes; Routing; Simulated annealing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1996., IEEE 39th Midwest symposium on

Conference_Location

Ames, IA

Print_ISBN

0-7803-3636-4

Type

conf

DOI

10.1109/MWSCAS.1996.594173

Filename

594173