Self-calibrating floating-point analog-to-digital converter

The floating-point analog-to-digital converter (FPADC) is an extended version of the fixed-point ADC. It is designed to deal with a broader dynamic range of signals while exhibiting a smaller relative quantization error. The traditional implementation of the FPADC requires high-precision high-speed components in order to achieve these characteristics for high sampling rates. The paper introduces a new high-speed high-precision FPADC that employs low-grade components whose errors are compensated through a low-speed high-precision calibration mechanism. The precision is maintained at high values by additional hardware that periodically performs calibration cycles. A hybrid hardware-software implementation of the design is carried out and described. Finally, experimental measurements are performed to compare the characteristics of the new FPADC.