AREA optimized low power arithmetic and logic unit

In this paper, we proposed a low power 1-bit full adder (FA) with 10-transistors and this is used in the design ALU. Various 16-bit ALUs are designed and compared. By using low power 1-bit full adder in the implementation of ALU, the power and area are greatly reduced to more than 70% compared to conventional design and 30% compared to transmission gates. So, the design is attributed as an area efficient and low power ALU. This design does not compromise for the speed as the delay of the full adder is minimized thus the overall delay. The leakage power of the design is also reduced by designing the full adder with less number of power supply to ground connections. In fact, power considerations have been the ultimate design criteria in special portable applications. For large number of computations, efficient ALU is to be designed for minimum area and low-power without compromising the high speed.