AREA and power optimized multipliers with minimum leakage

In this work, we designed a 10 transistor full adder for low power which is used in the implementation of different types of multipliers. All these multipliers are compared for different technologies 90nm, 70nm, 50nm. A power gating technique is used by placing an MTCMOS cell is used at fine grain level so as to minimize the leakage power. Multiplier is an essential arithmetic component for any DSP application, such as filtering and fast Fourier transform (FFT). To achieve high execution speed, parallel array multipliers are widely used. These multipliers tend to consume most of the power in DSP computations, and thus power-efficient multipliers are very important for the design of low-power DSP systems. Two Components contribute to the power dissipation in CMOS circuits. The Static dissipation is due to leakage current, while dynamic power dissipation is due to switching transient current as well as charging and discharging of load capacitances.