Title :
A hierarchical interconnection structure for field-programmable gate arrays
Author :
Ping-Tsung Wang ; Yen-Tai Lai ; Kun-Nen Chen
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Abstract :
A new interconnection structure for FPGAs is presented. The structure is hierarchically divided into two levels. Four adjacent logic blocks are grouped together at the first level, and then the group is connected to a bus structure at the second level. The functionality of a logic block is enhanced so that less logic blocks are needed and interconnections are simplified. Therefore, the performance of the FPGA is much improved.<>
Keywords :
hierarchical systems; logic arrays; logic design; network routing; FPGA; bus structure; configurable connection blocks; configurable logic blocks; enhanced functionality; field-programmable gate arrays; hierarchical interconnection structure; integrated circuit; performance; Adders; Capacitance; Field programmable gate arrays; Integrated circuit interconnections; Logic arrays; Logic circuits; Propagation delay; Routing; Switches; Wires;
Conference_Titel :
TENCON '93. Proceedings. Computer, Communication, Control and Power Engineering.1993 IEEE Region 10 Conference on
Conference_Location :
Beijing, China
Print_ISBN :
0-7803-1233-3
DOI :
10.1109/TENCON.1993.320050
