Title :
A new representation for programmable logic arrays to facilitate testing and logic design
Author :
Jing-Jou Tang ; Kuen-Jong Lee ; Bin-Da Liu
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Abstract :
Presents a new graph model and an associated set of operations for representing programmable logic arrays (PLAs). Through this graph model, most realistic PLA faults, including crosspoint, stuck-at, break and bridging faults, can be modeled. The work of diagnosis and test generation is thus simplified. Also, many logic design problems, such as folding, minimization and decomposition, can be done using this representation.<>
Keywords :
graph theory; logic arrays; logic design; logic testing; minimisation of switching nets; PLA representation scheme; break faults; bridging faults; crosspoint faults; decomposition; diagnosis; folding; graph model; logic design; minimization; operations; programmable logic arrays; stuck-at faults; test generation; testing; Bridge circuits; Circuit faults; Logic arrays; Logic circuits; Logic design; Logic devices; Logic testing; Matrix decomposition; Minimization; Programmable logic arrays;
Conference_Titel :
TENCON '93. Proceedings. Computer, Communication, Control and Power Engineering.1993 IEEE Region 10 Conference on
Conference_Location :
Beijing, China
Print_ISBN :
0-7803-1233-3
DOI :
10.1109/TENCON.1993.320051
