Title :
Block systolic computations in digital filters
Author_Institution :
Dept. of CES, Yuan-Ze Inst. of Technol., Chungli, Taiwan
Abstract :
Many efficient systolic algorithms in the block computation of digital filters have been derived. Highly concurrent structures can be implemented from these block systolic computation algorithms. All the performances of these highly concurrent structures can be described using the total computation times and the total processor numbers needed for each algorithm. A comparison with sequential algorithms using tables of speedup rates is presented, and the efficiency for each block algorithm is summarized.<>
Keywords :
digital filters; parallel algorithms; systolic arrays; algorithm efficiency; block systolic computations; computation times; digital filters; highly concurrent structures; parallel algorithms; performance; processor numbers; sequential algorithms; speedup rates; systolic array architecture; Computer architecture; Concurrent computing; Digital filters; Finite impulse response filter; Gold; High performance computing; Parallel algorithms; Parallel processing; Pipeline processing; Systolic arrays;
Conference_Titel :
TENCON '93. Proceedings. Computer, Communication, Control and Power Engineering.1993 IEEE Region 10 Conference on
Conference_Location :
Beijing, China
Print_ISBN :
0-7803-1233-3
DOI :
10.1109/TENCON.1993.320064
