Title :
Set-and-see switch-level simulation for VLSI functional verification
Author_Institution :
Dept. of Comput. Sci., Georgia Univ., Athens, GA, USA
Abstract :
An interactive “set-and-see” simulator combines the Magic VLSI layout editor [Ousterhout, et al., 1984] and the Esim switch-level simulator [Terman, 1983] in a unique way. From the layout editor, the designer can extract, flatten, and initialize the circuit for simulation. The designer can set logic values of nodes interactively and see the resulting (simulated) node values displayed directly on the layout. The set-and-see simulator suggests the same mode of operation with other editors/simulators
Keywords :
VLSI; circuit analysis computing; integrated circuit layout; integrated circuit modelling; Esim switch-level simulator; Magic VLSI layout editor; VLSI functional verification; interactive simulator; logic node values; set-and-see switch-level simulation; Circuit simulation; Computational modeling; Data mining; Logic testing; MOSFETs; Switches; Switching circuits; Tiles; Timing; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1996., IEEE 39th Midwest symposium on
Conference_Location :
Ames, IA
Print_ISBN :
0-7803-3636-4
DOI :
10.1109/MWSCAS.1996.594184
