A low power, self-biased, bandwidth tracking semi-digital PLL design

In a conventional charge-pump based PLL design, the loop parameters such as the bandwidth, jitter performance, charge-pump current, pull-in range among others govern the architecture and implementation details of the PLL. Different loop parameter specification change with a change in the reference frequency and in most cases, requires careful re-design of some of the PLL blocks. This paper describes the implementation of a semi-digital PLL for high bandwidth applications, which is self-biased, low-power and exhibits bandwidth tracking for all reference frequencies between 40 MHz and 2.5 GHz in 65nm CMOS technology. This design can be used for a wide range of reference frequencies without redesigning any block. The bandwidth can be fixed to some fraction of the reference frequency during design time. In this work, the PLL is designed to make the bandwidth track 1/20th of the reference frequency. Since this PLL is self-compensated, the PLL performance and the bandwidth remains the same over PVT corners.