DocumentCode
2040471
Title
An approach to realize the parallel real-time correlator based on parallel pipeline from addition network
Author
Zhang Jun ; Zhang Qishan
Author_Institution
Beijing Inst. of Aeronaut., China
Volume
2
fYear
1993
fDate
19-21 Oct. 1993
Firstpage
849
Abstract
A parallel correlator requires real time processing performance in many applications. Based on an analysis of the characteristics of a real-time digital correlator and a parallel PROM addition network, this paper presents a pipeline algorithm for a parallel PROM addition network and an architecture implementation algorithm for a fast parallel addition network and proposes an algorithm for constructing the data table of a parallel PROM addition unit. After the analysis, the design of a 32-64 bit full digital parallel real-time correlator is presented.<>
Keywords
PROM; adders; correlators; digital arithmetic; parallel architectures; real-time systems; synchronisation; 32 bit; 64 bit; addition network; data table; fast parallel addition; frame synchronizer; parallel PROM addition unit; parallel pipeline; parallel real-time correlator; Correlators; Detectors; PROM; Phase change random access memory; Pipelines; Zinc;
fLanguage
English
Publisher
ieee
Conference_Titel
TENCON '93. Proceedings. Computer, Communication, Control and Power Engineering.1993 IEEE Region 10 Conference on
Conference_Location
Beijing, China
Print_ISBN
0-7803-1233-3
Type
conf
DOI
10.1109/TENCON.1993.320146
Filename
320146
Link To Document