DocumentCode
2040509
Title
Using Multiple Scales Method to calculate threshold crossing time for the ramp response for high inductance VLSI interconnects
Author
Ligocka, Agnieszka ; Bandurski, Wojciech
Author_Institution
Poznan Univ. of Technol., Poznan
fYear
2008
fDate
12-15 May 2008
Firstpage
1
Lastpage
4
Abstract
The paper presents a new method of deriving the closed form formula for the output voltage and threshold crossing time for low-loss on-chip upper layer interconnects The threshold crossing time solution for the ramp excitation is derived. The calculation of output voltage of two coupled interconnects for the ramp input is also presented.
Keywords
VLSI; integrated circuit interconnections; coupled interconnects; inductance VLSI interconnects; low-loss on-chip upper layer interconnects; multiple scales method; ramp excitation; ramp response; threshold crossing time; Delay; Differential equations; Inductance; Integrated circuit interconnections; Inverters; Paper technology; Perturbation methods; Steady-state; Very large scale integration; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Propagation on Interconnects, 2008. SPI 2008. 12th IEEE Workshop on
Conference_Location
Avignon
Print_ISBN
978-1-4244-2317-0
Electronic_ISBN
978-1-4244-2318-7
Type
conf
DOI
10.1109/SPI.2008.4558391
Filename
4558391
Link To Document