Automated least-significant bit datapath optimization for FPGAs

Author

Chang, Mark L. ; Hauck, Scott

Author_Institution

Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA

fYear

2004

fDate

20-23 April 2004

Firstpage

59

Lastpage

67

Abstract

In this paper, we present a method for FPGA datapath precision optimization subject to user-defined area and error constraints. This work builds upon our previous research which presented a methodology for optimizing the dynamic range- the most significant bit position. In this work, we present an automated optimization technique for the least-significant bit position of circuit datapaths. We present results describing the effectiveness of our methods on typical signal and image processing kernels.

Keywords

adders; circuit optimisation; error analysis; field programmable gate arrays; image processing; simulated annealing; FPGA datapath precision optimization; automated optimization; circuit datapaths; error constraints; image processing kernels; least significant bit problem; signal processing kernels; Circuits; Constraint optimization; Dynamic range; Fabrics; Field programmable gate arrays; Hardware; Image processing; Optimization methods; Quantization; Signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Custom Computing Machines, 2004. FCCM 2004. 12th Annual IEEE Symposium on

Print_ISBN

0-7695-2230-0

Type

conf

DOI

10.1109/FCCM.2004.18

Filename

1364617