FPGA-based acceleration of the 3D finite-difference time-domain method

In order to take advantage of the significant benefits afforded by computational electromagnetic techniques, such as the finite-difference time-domain (FDTD) method, solvers capable of analyzing realistic problems in a reasonable time frame are required. Although software-based solvers are frequently used, they are often too slow to be of practical use. To speed up computations, hardware-based implementations of the FDTD method have been recently proposed. In this paper, we present our most recent progress in the area of FPGA-based 3D FDTD accelerators. Three aspects of the design are discussed, including the host-PC interface, memory hierarchy, and computational datapath. Implementation and benchmarking results are also presented, demonstrating that this accelerator is capable of at least three-fold speedups over thirty-node PC clusters.