Minimizing Power in Very-Low-Voltage Switched-Opamp Pipelined ADCs

In this paper, a design methodology for low-power design of very-low-voltage high-resolution switched-opamp ADCs (analog-to-digital converters) is presented. This methodology determines the optimum values of all stage capacitors, the compensation capacitors of the opamps and also the resolutions of the stages to minimize power consumption for an expected signal-to-noise ratio. The design procedure is applied to a 1-V 12-bit 10 MS/s pipelined ADC as a case study. The design challenges in very-low-voltage ADCs and the solutions are discussed. HSpice simulations of the 1-V ADC in a 0.18-¿m CMOS process confirm that the ADC effective number of bits is more than 11.1 bits for a 1.2-V 2-MHz input signal.