Title :
Successful implementation of AES algorithm in hardware
Author :
Borhan, R. ; Fuad Tengku Aziz, Raja Mohd
Author_Institution :
Integrated Circuit Dev., Kuala Lumpur, Malaysia
Abstract :
Implementation of AES algorithm in hardware always found its bottleneck during the key scheduling process as it involves a lot of multiplication steps. This paper discusses how this bottleneck is identified, ways to overcome them and the implementation of the said algorithm with the improvement of the key scheduling result to a successful AES hardware implementation in Verilog Language. Efficiency is described using the clock speed it can manage after successful synthesis of the said AES verilog codes.
Keywords :
cryptography; hardware description languages; processor scheduling; AES hardware implementation; AES verilog codes; Verilog Language; clock speed; hardware AES algorithm; key scheduling process; AES; Verilog; cryptography; key scheduling; synthesis;
Conference_Titel :
Electronics Design, Systems and Applications (ICEDSA), 2012 IEEE International Conference on
Conference_Location :
Kuala Lumpur
Print_ISBN :
978-1-4673-2162-4
DOI :
10.1109/ICEDSA.2012.6507810
