A study of signed multipliers on FPGAs

Multiplication is an important fundamental operation that is critical in most signal and image processing applications. It is also essential for all types of wireless communications applications. We compare general multipliers from an architecture point of view, maximum clock frequency, latency, throughput, resource usage, as well as dynamic power consumption. We use a flopped combinational baseline multiplier for our comparison and we use the same FPGA platform to be fair in our analysis. We conclude that the regular approach of implying the use of DSP elements in the HDL code is not the best.