Title :
A study of signed multipliers on FPGAs
Author :
Aly, Mohamed ; Sayed, Ali
Author_Institution :
Digital Design Dept., Varkon Semicond., Cairo, Egypt
Abstract :
Multiplication is an important fundamental operation that is critical in most signal and image processing applications. It is also essential for all types of wireless communications applications. We compare general multipliers from an architecture point of view, maximum clock frequency, latency, throughput, resource usage, as well as dynamic power consumption. We use a flopped combinational baseline multiplier for our comparison and we use the same FPGA platform to be fair in our analysis. We conclude that the regular approach of implying the use of DSP elements in the HDL code is not the best.
Keywords :
combinational circuits; digital signal processing chips; field programmable gate arrays; multiplying circuits; DSP elements; FPGA platform; HDL code; clock frequency; dynamic power consumption; flopped combinational baseline multiplier; image processing applications; signal processing applications; signed multipliers; wireless communication applications; Computer arithmetic; FPGA; Low power; Multiplier; VHDL; Verilog;
Conference_Titel :
Electronics Design, Systems and Applications (ICEDSA), 2012 IEEE International Conference on
Conference_Location :
Kuala Lumpur
Print_ISBN :
978-1-4673-2162-4
DOI :
10.1109/ICEDSA.2012.6507811
