Hardware-in-the-loop evolution of a 3-bit multiplier

Author

Larchev, Gregory V. ; Lohn, Jason D.

Author_Institution

QSS Group Inc., NASA Ames Res. Center, Moffett Field, CA, USA

fYear

2004

fDate

20-23 April 2004

Firstpage

277

Lastpage

278

Abstract

In this paper, we focus on evolving a 3-bit multiplier from scratch. This method assume a dual-redundant FPGA system whereby the faulty FPGA undergoes evolution to recover its functionality, while the redundant FPGA maintains proper functionality during an evolution of the faulty FPGA. After the fault is detected, redundancy is lost for a short period of time and restored. The multiplier design is purely combinational, so that no feedbacks are allowed and can potentially take up to 48 LUTs. ECJ a Java-based evolutionary computation and genetic programming system is used for task like decoding.

Keywords

combinational circuits; fault tolerance; field programmable gate arrays; genetic algorithms; multiplying circuits; redundancy; 3-bit multiplier design; Java based evolutionary computation; combinational circuits; decoding; dual redundant FPGA; fault tolerance; genetic programming system; hardware-in-the-loop evolution; redundancy; Circuit faults; Circuit testing; Evolutionary computation; Fault tolerance; Field programmable gate arrays; Hardware; NASA; Routing; Signal processing algorithms; Space vehicles;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Custom Computing Machines, 2004. FCCM 2004. 12th Annual IEEE Symposium on

Print_ISBN

0-7695-2230-0

Type

conf

DOI

10.1109/FCCM.2004.39

Filename

1364640