DocumentCode
2041214
Title
Opens board test coverage: when is 99% really 40%?
Author
Tegethoff, Mick M V ; Parker, Kenneth P. ; Lee, Ken
Author_Institution
Manuf. Test Div., Hewlett-Packard Co., Loveland, CO, USA
fYear
1996
fDate
20-25 Oct 1996
Firstpage
333
Lastpage
339
Abstract
In this paper we discuss board test coverage of opens for power pins of large ASICs soldered to electronic boards. Multiple power pin connections cannot be tested by typical electrical testing techniques because they are connected in parallel between the package and the board. We present in this paper an estimate of the probability of these power pin opens, outline the impact of the lack of test coverage in system performance, and offer possible solutions to the problem,
Keywords
application specific integrated circuits; integrated circuit testing; printed circuit testing; probability; statistical analysis; IC power pins; board-mounted ASIC; electrical testing; electronic boards; large ASICs; multiple power pin connections; opens board test coverage; probability; Circuit faults; Circuit testing; Electronic equipment testing; Electronics packaging; Frequency; Laboratories; Pins; Power supplies; Power system modeling; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1996. Proceedings., International
Conference_Location
Washington, DC
ISSN
1089-3539
Print_ISBN
0-7803-3541-4
Type
conf
DOI
10.1109/TEST.1996.556979
Filename
556979
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