Title :
An FPGA interpolation processor for soft-decision Reed-Solomon decoding
Author :
Gross, Warren J. ; Kschischang, Frank R. ; Gulak, P. Glenn
Author_Institution :
Dept. of Electr. & Comput. Eng., McGill Univ., Montreal, Que., Canada
Abstract :
We propose a parallel architecture for implementing the interpolation step in the Koetter-Vardy soft-decision Reed-Solomon decoding algorithm. The key feature is the embedding of both a binary tree and a linear array into a two-dimensional array processor, enabling fast polynomial evaluation operations. An FPGA interpolation processor was implemented and demonstrated at a clock frequency of 23 MHz, corresponding to decoding rates of 10-15 Mbps.
Keywords :
Reed-Solomon codes; binary codes; decoding; field programmable gate arrays; interpolation; parallel architectures; polynomials; 23 MHz; FPGA interpolation processor; Koetter-Vardy soft decision algorithm; Reed-Solomon decoding; binary tree; linear array; parallel architecture; polynomial evaluation; two dimensional array processor; Binary trees; Clocks; Decoding; Field programmable gate arrays; Frequency; Interpolation; Parallel architectures; Parallel processing; Polynomials; Reed-Solomon codes;
Conference_Titel :
Field-Programmable Custom Computing Machines, 2004. FCCM 2004. 12th Annual IEEE Symposium on
Print_ISBN :
0-7695-2230-0
DOI :
10.1109/FCCM.2004.16
