DocumentCode
2041648
Title
A reconfigurable SoC architecture and caching scheme for 3D medical image processing
Author
Li, Jianchun ; Papachristou, Christos ; Shekhar, Raj
Author_Institution
Case Western Reserve Univ., Cleveland, OH, USA
fYear
2004
fDate
20-23 April 2004
Firstpage
320
Lastpage
321
Abstract
This paper deals with the reconfigurable SoC (system-on-chip) architecture and a 3D caching scheme targeted to Virtex II Pro FPGAs, to accelerate a broad range of 3D medical imaging algorithms. To achieve high computational bandwidth, architectural parallelisms are exploited at three different levels: brick operation cycle, multiple parallel data-stream processing and deep pipeline architecture for data-stream processing.
Keywords
cache storage; field programmable gate arrays; medical image processing; pipeline processing; reconfigurable architectures; system-on-chip; 3D caching scheme; 3D medical image processing; Virtex II Pro FPGA; architectural parallelisms; brick operation cycle; multiple parallel data stream processing; pipeline architecture; reconfigurable SoC architecture; system-on-chip architecture; Acceleration; Bandwidth; Biomedical image processing; Biomedical imaging; Computer architecture; Concurrent computing; Field programmable gate arrays; Parallel processing; Pipelines; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Field-Programmable Custom Computing Machines, 2004. FCCM 2004. 12th Annual IEEE Symposium on
Print_ISBN
0-7695-2230-0
Type
conf
DOI
10.1109/FCCM.2004.8
Filename
1364658
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