Improvement of pick & place yield in carrier tape packaging system through materials selection and cavity structure optimization

Pick & place yield performance is among of the most important parameters for electronic components assembly, especially for today´s miniaturized packages. For very small devices such as small outline transistor (SOT) with carrier tape packaging system, sticking of device on cover tape was often observed, which is believed to be caused by accumulated electrostatic charge on the surfaces of device and cover tape. To improve pick & place yield performance, electrostatic charges and electrostatic forces should be minimized. In this work, pick and place tests were performed for SOT devices packaged in different packaging systems using different materials and cavity structures. The results show that the pick & place yield can be significantly improved by the right material selection and cavity structure optimization. The relationships among material property, cavity structure, electrostatic charge, electrostatic force, pick & place yield were correlated, based on experimental tests and finite elemental simulation. This work would provide test and simulation methodologies and guidelines for materials selection and cavity structure design for carrier tape packaging systems.