• DocumentCode
    2041884
  • Title

    Clock period optimization technique using multiple clocking domains

  • Author

    Nesamani, I. Flavia Princess ; Priyadarshini, K. Mariya ; Devi, A. Sri ; Prabha, V. Lakshmi

  • Author_Institution
    ECE Dept, Karunya Univ., Coimbatore, India
  • Volume
    4
  • fYear
    2011
  • fDate
    8-10 April 2011
  • Firstpage
    335
  • Lastpage
    339
  • Abstract
    The concept of unconstrained clock skew scheduling (CSS) is practically limited due to the difficulties in implementing dedicated clock delays in a reliable manner. This results in a significant limitation of the optimization potential. As an alternative the application of multiple clocking domains with dedicated clock buffer will be implemented. In this paper, an algorithm is proposed for determining the minimum number of clock domains to be used for multi domain clock skew scheduling. The concept of multi domain clock skew scheduling is implemented on the bench mark circuit and the same is applied to digital logic circuit of the telephone answering machine.
  • Keywords
    buffer circuits; clocks; delays; logic circuits; optimisation; scheduling; benchmark circuit; clock buffer; clock delay; clock period optimization technique; digital logic circuit; multidomain CSS; multidomain clock skew scheduling; telephone answering machine; Cascading style sheets; Clocks; Delay; Flip-flops; Optimization; Scheduling; Synchronization; Clock skew; Low Power VLSI; Synopsys Design Compiler; clock skew scheduling (CSS);
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics Computer Technology (ICECT), 2011 3rd International Conference on
  • Conference_Location
    Kanyakumari
  • Print_ISBN
    978-1-4244-8678-6
  • Electronic_ISBN
    978-1-4244-8679-3
  • Type

    conf

  • DOI
    10.1109/ICECTECH.2011.5941915
  • Filename
    5941915