Title :
On cancelling the effects of logic sharing for improved path delay fault testability
Author :
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
Abstract :
Sharing of logic among the various primary outputs of a circuit reduces the overall size of the circuit. However, shared logic may have adverse effects on the number of paths and on the path delay fault testability of the circuit. In this work, we propose a procedure to reverse the effects of logic sharing when it causes a significant increase in the number of paths and a significant reduction in testability. Experimental results show that the proposed procedure is an effective preprocessing step of global optimization, that increases the effectiveness of resynthesis procedures based on local transformations
Keywords :
circuit optimisation; delays; design for testability; fault diagnosis; logic design; logic testing; global optimization; improved path delay fault testability; local transformations; logic sharing; path delay fault testability; preprocessing; resynthesis; shared logic; Circuit faults; Circuit synthesis; Circuit testing; Cities and towns; Delay effects; Electrical fault detection; Fault detection; Logic circuits; Logic testing; Timing;
Conference_Titel :
Test Conference, 1996. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-3541-4
DOI :
10.1109/TEST.1996.556982
