Efficient execution of process networks on a reconfigurable hardware virtual machine

Author

Dyer, Matthias ; Platzner, Marco ; Thiele, Lothar

Author_Institution

Lab. of Comput. Eng. & Networks, Swiss Fed. Inst. of Technol., Zurich, Switzerland

fYear

2004

fDate

20-23 April 2004

Firstpage

342

Lastpage

344

Abstract

In this paper, we present a novel use of an FPGA as a computing element for streaming based application. We investigate the virtualized execution of dynamic reconfigurable tasks. We use the process networks model as a coordination language which is interpreted on a virtual machine run-time system. We present and discuss the results of a design space exploration, which evaluates the performance of the system architecture for different configurations.

Keywords

field programmable gate arrays; processor scheduling; reconfigurable architectures; virtual machines; FPGA; coordination language; design space exploration; dynamic reconfigurable tasks; performance evaluation; process networks; processor scheduling; reconfigurable hardware virtual machine; system architecture; virtual machine run time system; virtualized execution; Algorithm design and analysis; Application software; Application virtualization; Computer architecture; Computer networks; Field programmable gate arrays; Hardware; Programming profession; Space exploration; Virtual machining;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Custom Computing Machines, 2004. FCCM 2004. 12th Annual IEEE Symposium on

Print_ISBN

0-7695-2230-0

Type

conf

DOI

10.1109/FCCM.2004.31

Filename

1364669