A 3D integration testing vehicle with TSV interconnects

3D integration is one of the potential solutions for extending Moore´s momentum in the next decennium. Through silicon via (TSV) is a key interconnect technology for future´s higher performance and system integration with vertical stacked chips in package, which can achieve smaller interconnection delay, heterogeneous technologies integration and potentially lower cost and reduce time-to-market. In this paper, a testing vehicle of 3D stacking dies with TSVs as the major interconnect was designed. A dummy die with 5 μm diameter TSVs was fabricated and assembled on a silicon interposer, which has TSVs as well. The dummy die/chip was bonded on the interposer through Cu-Sn-Cu bonding at 280°C, and then, the bonded module was assembled on designed testing board.