Title :
Circuit partitioning for multiprocessor SPICE
Author :
Jia, X.D. ; Chen, R.M.M. ; Layfield, A.M.
Author_Institution :
Dept. of Electron. Eng., City Polytech. of Hong Kong, Kowloon, Hong Kong
Abstract :
Circuit partitioning issues for circuit simulation on distributed multiprocessors are discussed in this paper. An efficient three level partitioning algorithm for large-scale circuit is proposed. Using this algorithm, we can partition a large-scale circuit into r sub-circuits of similar size while keeping the interconnect set to a minimum. This algorithm may also be implemented in parallel. An example is provided to show the performance of the algorithm.<>
Keywords :
SPICE; circuit analysis computing; multiprocessing systems; circuit partitioning; circuit simulation; distributed multiprocessors; interconnect set; large-scale circuit; multiprocessor SPICE; performance; Circuit simulation; Circuit synthesis; Computational modeling; Equations; Integrated circuit interconnections; Large-scale systems; Parallel processing; Partitioning algorithms; SPICE; Very large scale integration;
Conference_Titel :
TENCON '93. Proceedings. Computer, Communication, Control and Power Engineering.1993 IEEE Region 10 Conference on
Conference_Location :
Beijing, China
Print_ISBN :
0-7803-1233-3
DOI :
10.1109/TENCON.1993.320216
