DocumentCode :
2042239
Title :
Silicon substrate with TSV for light emitting diode packaging
Author :
Zhicheng Lv ; Xiaogang Liu ; Liang Yang ; Jiaojiao Yuan ; Xuefang Wang ; Sheng Liu
Author_Institution :
Sch. of Optoelectron. Sci. & Eng., Huazhong Univ. of Sci. & Technol., Wuhan, China
fYear :
2012
fDate :
13-16 Dec. 2012
Firstpage :
1
Lastpage :
4
Abstract :
In this paper, a novel substrate for white light LED (light emitting diode) is presented, the silicon substrate in which silicon wafer with cavities and TSVs (through silicon via). The fabrication process begins with double-side polished 4-inch silicon wafer. Firstly a silicon dioxide layer with 0.8μm thickness is formed on the silicon wafer through thermal oxidation. Then the photo-resistor layer with patterns on both sides of the wafer is carried out using lithography. The following step is to open silicon dioxide windows by performing RIE (reactive ion etching) on both sides of the wafer. After RIE process the wafer is sent into KOH bath for wet etching to form cavities and TSVs. Additional thermal oxidation process for electrical insulation is needed to cover the silicon, which is exposed in the wet etching step. Sputtering is used to form copper seed layer on both sides of the wafer. Copper layer is thickened and TSVs are filled by electroplating. After lithography, silver layer is sputtered on the cavity side of the wafer for LED chip mounting, wire bonding and forming side wall mirror. The copper layer area not wanted is etched away in FeCl3 solution. Blue LED chip is then mounted onto the substrate using solder by reflow process in the cavity. Yellow phosphor and epoxy mixture is then printed into the cavity to cover the LED chip for color turning. This method offers a structure with low profile and compact for LED wafer level packaging. Experimental results verify the feasibility of proposed method.
Keywords :
electroplating; elemental semiconductors; lead bonding; light emitting diodes; oxidation; photolithography; reflow soldering; silicon; silicon compounds; sputter etching; three-dimensional integrated circuits; wafer level packaging; KOH bath; LED chip mounting; LED wafer level packaging; RIE process; Si; SiO2; TSV; blue LED chip; color turning; copper seed layer; double-side polished silicon wafer; electrical insulation; electroplating; epoxy mixture; fabrication process; light emitting diode packaging; lithography; photoresistor layer; reactive ion etching; reflow soldering process; side wall mirror; silicon substrate; silicon wafer; silver layer; size 0.8 mum; size 4 inch; sputtering; thermal oxidation process; through silicon via; wet etching; white light LED; wire bonding; yellow phosphor;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Materials and Packaging (EMAP), 2012 14th International Conference on
Conference_Location :
Lantau Island
Print_ISBN :
978-1-4673-4945-1
Electronic_ISBN :
978-1-4673-4943-7
Type :
conf
DOI :
10.1109/EMAP.2012.6507853
Filename :
6507853
Link To Document :
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