High-speed, low-power device trend and low-k layer delamination

Flipchip is one of the key technologies that offer lower parasitic impedance and better power delivery to compensate reducing margins between power and threshold voltages with. The roadmap of core voltage is shown in Fig. 1 cited from the Japan Jisso Technology Roadmap (JJTR 2011, [1]). Requirements and trends of electronic systems are surveyed every other year in Japan and broken down to the parameters by JJTR Committee of Japan Electronics and Information Technology Industries Association (JEITA). The introduction of fragile low-k layers and lead-free solder bumps with higher Young´s modulus into a die has made chip-package interaction critical. Delamination of low-k layer on a flipchip die can be seen as white spots (white bumps) in the image of scanning acoustic tomography (SAT). This paper introduces the countermeasures against white bumps during flipchip bonding and reflowing process.