A BIST methodology for comprehensive testing of ram with reduced heat dissipation

The severity of excessive heat dissipation during concurrent BIST of memory modules has been documented by V. Zorian ["A Distributed BIST Control Scheme For Complex VLSI Devices," IEEE VLSI Test Symposium, Mar. 1993, pp 4-9]. In this paper, we present new versions of several memory tests that reduce heat dissipation during testing. Each proposed test has the same fault coverage and time complexity as the original version but it reduces heat dissipation by a factor of two or more. For three of the tests, the heat dissipation is reduced by factors of four to sixteen. The design of BIST circuitry required to implement the proposed tests are presented and it is shown that additional area overhead incurred is very small.