DocumentCode
2042789
Title
HOOVER: hardware object-oriented verification
Author
Aref, Mostafa M. ; Elleithy, Khaled M.
Author_Institution
Dept. of Inf. & Comput. Sci., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia
fYear
1998
fDate
19-21 Feb 1998
Firstpage
351
Lastpage
355
Abstract
In this paper a new formal hardware verification approach based on object oriented techniques is presented. The HOOVER system (Hardware Object Oriented VERification) is described. A cell library of different hardware components has been implemented as classes. Components in the cell library are described at the transistor level, gate level, logical level, and functional level. The verification of a CMOS inverter and 1-bit CMOS adder using HOOVER is given in the paper
Keywords
circuit CAD; digital integrated circuits; formal verification; integrated circuit design; logic CAD; object-oriented methods; HOOVER system; cell library; formal hardware verification; functional level; gate level; hardware object-oriented verification; logical level; transistor level; Computer science; Encapsulation; Formal verification; Hardware; Inverters; Libraries; Logic; Object oriented modeling; Petroleum; Specification languages; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 1998. Proceedings of the 8th Great Lakes Symposium on
Conference_Location
Lafayette, LA
ISSN
1066-1395
Print_ISBN
0-8186-8409-7
Type
conf
DOI
10.1109/GLSV.1998.665308
Filename
665308
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