• DocumentCode
    20431
  • Title

    UNIVERCM: The UNIversal VERsatile Computational Model for Heterogeneous System Integration

  • Author

    Di Guglielmo, Luigi ; Fummi, Franco ; Pravadelli, Graziano ; Stefanni, Francesco ; Vinco, Sara

  • Author_Institution
    Dept. of Comput. Sci., Univ. of Verona, Verona, Italy
  • Volume
    62
  • Issue
    2
  • fYear
    2013
  • fDate
    Feb. 2013
  • Firstpage
    225
  • Lastpage
    241
  • Abstract
    Designers are more and more forced to define innovative models and methodologies for managing integration of heterogeneous components and heterogeneous Chip Multiprocessors (CMPs) in modern embedded systems. In this context, component-based design seems the more promising approach, but it suffers from the lack of a widely adopted Model of Computation (MoC) able to capture component heterogeneity. This paper proposes univerCM, a new model of computation based on the Heterogeneous Intermediate Format (HIF) with the aim of supporting bottom-up design and system integration from a set of heterogeneous components. HW and SW components can be described by means of different languages and according to different MoCs, toward a uniform intermediate description based on a rigorous semantics. A mapping from univerCM to SystemC is proposed then to obtain a homogeneous description intended for fast simulation, that can be also used as starting point for CMP design flows. Experimental results show the effectiveness of univerCM in managing system heterogeneity.
  • Keywords
    embedded systems; hardware description languages; microprocessor chips; multiprocessing systems; CMP design flow; HIF; HW component; MoC; SW component; SystemC; component heterogeneity; component-based design; embedded system; heterogeneous chip multiprocessor; heterogeneous component; heterogeneous intermediate format; heterogeneous system integration; homogeneous description; innovative model; model of computation; univerCM; universal versatile computational model; Automata; Computational modeling; Delay; Semantics; Syntactics; Valves; Wires; Formal specifications; electronic design automation; modeling; multiprocessor; simulation;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.2012.156
  • Filename
    6226366