A New Architecture for Reducing Phase Noise of Digital Carrier Recovery Algorithms in High-Order QAM Demodulators

In this paper a new architecture for reducing the phase noise of digital carrier recovery (CR) algorithms is proposed. This architecture is useful for high-order QAM modulations in which very fine phase noise characteristic is needed for RF oscillators and for IF digital down converters (DDC). Using software aided algorithm, this architecture can be utilized in all digital CR algorithms to enhance their equivalent phase noise, making them almost independent of their loop filter performance. Simulations show a phase noise enhancement of about 20 dB compared to basic CR algorithms, allowing the designers to use simpler phase estimations techniques for demodulators.