Design and Optimization of Digital Signal Components Separator of LINC Transmitters Using FPGA Processors

This paper presents a comparative study of the performances of various digital signal components separator topologies for linear amplification using non linear components based transmitters. The topologies studied use different subcomponents to perform the most computationally demanding part of the digital signal components separator that is the calculation of the square root function. Three cases are considered: the square root function is implemented using a commercially available square root mega-function, a custom designed square root function, and a one dimensional look-up table. The measurement results show that all topologies achieve comparable throughput performances. However, the look-up table implementation reduces the computational complexity and improves the achievable accuracy.