A sliding-DFT based power-line phase measurement algorithm and its FPGA implementation

This paper proposes a power-line phase measurement algorithm which is based on the recursive implementation of sliding-DFT. The algorithm is designed to have a robust behavior against the erroneous factors of frequency drift, additive noise, and twiddle factor approximation. The size of the phase error caused by the finite wordlength implementation of DFT twiddle factors is shown to be significantly lower than that of magnitude error. The drastic reduction of the phase error is achieved by the exploitation of the quadruplet symmetry characteristics of the approximated twiddle factors in the complex plane. Four channel power-line phase measurement system is also designed and implemented based on the time-multiplexed sharing architecture of the proposed algorithm under the Xilinx FPGA system. The operation of the developed system is also verified by the experiment performed under the test environment implemented with the multi-channel function generator and the on-line interfaced host processor system. The proposed algorithm´s features of phase measurement accuracy and its robustness against the finite wordlength effects can provide a significant impact, especially for the ASIC or microprocessor based embedded system applications, where the enhanced processing speed and implementation simplicity are crucial design considerations.