DocumentCode
2045837
Title
2D defragmentation heuristics for hardware multitasking on reconfigurable devices
Author
Septién, Julio ; Mecha, Hortensia ; Mozos, Daniel ; Tabero, Jesús
Author_Institution
Univ. Complutense de Madrid, Spain
fYear
2006
fDate
25-29 April 2006
Abstract
This paper focuses on the fragmentation problem produced in 2D run-time reconfigurable FPGAs when hardware multitasking management is considered. Though allocation heuristics can take fragmentation into account when a new task arrives, the free area becomes inevitably fragmented as the tasks finish and exit the FPGA. The main contributions of our work are a fragmentation metric able to estimate when the FPGA fragmentation status has become critical, and several heuristics to decide when to perform defragmentation and how to perform it. This defragmentation heuristics can be of a preventive kind, driven by alarms that fire when isolated islands appear or a high fragmentation status is reached. It can be also an on-demand process produced when a task allocation fails though there is enough free area in the FPGA to accommodate it.
Keywords
field programmable gate arrays; reconfigurable architectures; 2D defragmentation heuristics; 2D runtime reconfigurable FPGA; hardware multitasking management; reconfigurable device; Field programmable gate arrays; Fires; Hardware; Multiprocessor interconnection networks; Multitasking; Resource management; Runtime; Time factors;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel and Distributed Processing Symposium, 2006. IPDPS 2006. 20th International
Print_ISBN
1-4244-0054-6
Type
conf
DOI
10.1109/IPDPS.2006.1639432
Filename
1639432
Link To Document