Title :
SEU tolerant device, circuit and processor design
Author :
Heidergott, William
Author_Institution :
Gen. Dynamics C4 Syst., Scottsdale, AZ, USA
Abstract :
Development of highly reliable and available systems requires consideration of the occurrence of single event upsets, the effects they have on system performance, and strategies for their prevention and mitigation. Methods of systems engineering process and the application and validation of techniques for fault tolerance are discussed as elements in the elimination and mitigation of single event upsets.
Keywords :
circuit reliability; error correction codes; error detection codes; fault tolerance; microprocessor chips; radiation effects; SEU tolerant device; error correction coding; error detection; fault avoidance; fault masking; fault tolerance; fault tolerant system; modular redundancy; processor design; radiation effects; single event upset; soft error rate; temporal redundancy; Aerospace electronics; Circuit faults; Error analysis; Error correction; Error correction codes; Fault detection; Fault tolerant systems; Process design; Redundancy; Single event upset;
Conference_Titel :
Design Automation Conference, 2005. Proceedings. 42nd
Print_ISBN :
1-59593-058-2
DOI :
10.1109/DAC.2005.193763
