DocumentCode
2046323
Title
Layout optimization to reduce EMI of a switched mode power supply
Author
Schanen, Jean Luc ; Jourdan, Ludovic ; Roudet, James
Author_Institution
Lab. d´´Electrotechnique de Grenoble, ENSIEG, Grenoble, France
Volume
4
fYear
2002
fDate
2002
Firstpage
2021
Lastpage
2026
Abstract
This paper shows how to reach the "best" possible layout, satisfying simultaneously the minimal surface, all technological constraints due to the geometry of the components, and a reduced EMC signature. For this purpose, all components must be modeled in the high frequency domain, including interconnects. An interesting harmonic approach is used to predict EMI spectrum, which avoids the prohibitive computation times induced by temporal simulation. Therefore, optimization results are nearly instantaneous using a simple Mathcad® sheet. This method is illustrated in the case of a 14 V-42 V boost converter, realized on IMS
Keywords
DC-DC power convertors; circuit layout; electromagnetic interference; interconnections; switched mode power supplies; 14 V; 42 V; EMI reduction; EMI spectrum prediction; Mathcad sheet; SMPS EMI reduction by layout optimisation; boost converter; components geometry; harmonic approach; high frequency domain; interconnects; layout optimization; prohibitive computation times; reduced EMC signature; switched mode power supply; temporal simulation; Capacitors; Circuit simulation; Electromagnetic compatibility; Electromagnetic interference; Frequency domain analysis; Geometry; Insulation life; Integrated circuit interconnections; Predictive models; Switched-mode power supply;
fLanguage
English
Publisher
ieee
Conference_Titel
Power Electronics Specialists Conference, 2002. pesc 02. 2002 IEEE 33rd Annual
Conference_Location
Cairns, Qld.
Print_ISBN
0-7803-7262-X
Type
conf
DOI
10.1109/PSEC.2002.1023111
Filename
1023111
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