Investigation into programmability for layer 2 protocol frame delineation architectures

Author

Toal, Ciaran ; Sezer, Sakir

Author_Institution

Inst. of Commun. & Inf. Technol., Queen´´s Univ. Belfast

fYear

2006

fDate

25-29 April 2006

Abstract

This paper presents the design and study of reconfigurable architectures for two data-link layer frame delineation techniques used for ATM and GFP. The architectures are targeted to Altera Stratix II FPGA technology and are investigated in terms of performance and area. This work addresses the potential for incorporating programmability into custom purpose architectures that could enable the same processing hardware to be used for processing multiple protocols

Keywords

asynchronous transfer mode; field programmable gate arrays; reconfigurable architectures; Altera Stratix II FPGA technology; asynchronous transfer mode; data-link layer frame delineation technique; generic frame procedure; protocol frame delineation architecture; reconfigurable architecture; Circuits; Cyclic redundancy check; Field programmable gate arrays; Hardware; Information technology; Payloads; Performance analysis; Physical layer; Protocols; Reconfigurable architectures;

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel and Distributed Processing Symposium, 2006. IPDPS 2006. 20th International

Conference_Location

Rhodes Island

Print_ISBN

1-4244-0054-6

Type

conf

DOI

10.1109/IPDPS.2006.1639460

Filename

1639460

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2046575