Title :
Exact aliasing computation for RAM BIST
Author :
Kebichi, O. ; Nicolaidis, M. ; Yarmolik, V.N.
Author_Institution :
Reliable Integrated Syst. Group, TIMA/INPG, Grenoble, France
Abstract :
In this paper we illustrate that exact aliasing computation in RAM BIST can be achieved with respect to accurate RAM fault models including single and multiple stuck-at, transition and coupling cell-array faults and decoder stuck-at faults
Keywords :
SRAM chips; built-in self test; decoding; fault diagnosis; logic testing; polynomials; random-access storage; RAM BIST; RAM fault models; corrective computation; coupling cell-array faults; decoder stuck-at faults; double faults; error polynomials; exact aliasing computation; multiple stuck-at faults; quadruple faults; single stuck-at cell-array faults; transition cell-array faults; triple faults; word oriented RAM; Application specific integrated circuits; Built-in self-test; Circuit faults; Circuit testing; Compaction; Decoding; Microprocessors; Random access memory; Read-write memory; Reliability engineering;
Conference_Titel :
Test Conference, 1995. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2992-9
DOI :
10.1109/TEST.1995.529813
