DocumentCode
2046598
Title
Multi-level reconfigurable architectures in the switch model
Author
Lange, Sebastian ; Middendorf, Martin
Author_Institution
Dept. of Comput. Sci., Leipzig Univ., Germany
fYear
2006
fDate
25-29 April 2006
Abstract
In this paper, we study multi-level dynamically reconfigurable architectures. These are extensions of standard reconfigurable architectures where ordinary reconfiguration operations correspond to the lowest reconfiguration level. On each higher reconfiguration level the reconfiguration capabilities of the reconfigurable resources that are available on the level directly below can be reconfigured. We show that the problem to find optimal reconfigurations with an arbitrary number of reconfiguration levels can be found in polynomial time for the switch cost model. The problem of finding the optimal number of reconfiguration levels is shown to be solvable in polynomial time on homogeneous multi-level architectures but it becomes NP-hard for heterogeneous multi-level architectures. Moreover, we present experimental results for some example problems on a simple test architecture.
Keywords
computational complexity; polynomials; reconfigurable architectures; NP-hard problem; heterogeneous multilevel architecture; homogeneous multilevel architecture; multilevel dynamically reconfigurable architecture; polynomial time; switch cost model; Computer architecture; Computer science; Cost function; Partitioning algorithms; Polynomials; Random access memory; Reconfigurable architectures; Switches; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel and Distributed Processing Symposium, 2006. IPDPS 2006. 20th International
Print_ISBN
1-4244-0054-6
Type
conf
DOI
10.1109/IPDPS.2006.1639461
Filename
1639461
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