Upset-tolerant CMOS SRAM using current monitoring: prototype and test experiments

Author

Calin, Th ; Vargas, F.L. ; Nicolaidis, M.

Author_Institution

TIMA/INPG, Grenoble, France

fYear

1995

fDate

21-25 Oct 1995

Firstpage

45

Lastpage

53

Abstract

This paper presents implementation and test experiments of a current monitoring technique for on-line detection and correction of transient faults in CMOS static RAMs. This technique combines built-in current sensing (BICS) with parity code to achieve zero detection latency and single-bit error correction

Keywords

CMOS memory circuits; SRAM chips; VLSI; computerised monitoring; electric current measurement; error correction; fault diagnosis; fault tolerant computing; integrated circuit testing; logic testing; monitoring; random-access storage; transient analysis; BICS; CMOS static RAM; SRAM; built-in current sensing; correction; current monitoring; online detection; parity code; prototype; single-bit error correction; test experiments; transient faults; upset-tolerant CMOS SRAM; zero detection latency; Circuit faults; Circuit testing; Delay; Electromagnetic transients; Error correction codes; Fault detection; Monitoring; Prototypes; Random access memory; Read-write memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1995. Proceedings., International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-7803-2992-9

Type

conf

DOI

10.1109/TEST.1995.529816

Filename

529816