Innovative early stage CPS (Chip-Package-System) co-design methodology

Recently system-on-chip (SoC) technology has been grown rapidly, and many function blocks are integrated in one-chip as solution. Then, core power in SoC draws much more current to supply the function blocks which execute complex and various operations, and the development of the process technology allows a lower supply voltage of SoC. As the current consumption increases and supply voltage decreases, the importance for the integrity of the power is strengthened. When the design of power-delivery-network (PDN) does not meet power-integrity (PI) characteristics, it may cause a malfunction of SoC and generate noise source which results in various electromagnetic interference (EMI) problems. In addition, the PDN design is distributed in several domains which are chip (or die)-level, package-level, and system-level, and there are contradictory constraint conditions between the domains. Since it is difficult to change IC design after established because of cost problem, robust PI characteristics in PDN design is required in the early stage of development. This paper provides the methodology to optimize PI characteristics such as the impedance and the static voltage-drop (or DC IR-drop) of PDN at the early stage of development cycle. Besides this methodology inspires a systematic perspective into designers to determine the number of power/ground balls in ball grid array (BGA) package, decoupling capacitors (or decaps) on printed circuit board (PCB), and vias on a package or a PCB. In this paper, two cases are carried out with ANSYS Siwave by the proposed method. As a result the number of power/ground balls is reduced to 61.5% for a bond-wire type package, and 87.5% for flip-chip type package than the conventional design respectively. At the same time, only with 53.9% and 82.4% number of decoupling capacitors, 53.9% and 84.1% number of vias in PCB, and 55.6% and 80.1% vias in package are used keeping PI characteristics such as power impedance and static voltage-drop (or D- IR-drop) compared to the conventional design.