• DocumentCode
    2046811
  • Title

    Response compaction with any number of unknowns using a new LFSR architecture

  • Author

    Volkerink, Erik H. ; Mitra, Subhasish

  • Author_Institution
    Agilent Labs., Palo Alto, CA, USA
  • fYear
    2005
  • fDate
    13-17 June 2005
  • Firstpage
    117
  • Lastpage
    122
  • Abstract
    This paper presents a new test response compaction technique with any number of unknown logic values (X´s) in the test response bits. The technique leverages an X-tolerant response compactor (X-compact), and forces X´s that are not tolerated by X-Compact to known values. The data required to designate the X´s not tolerated by the X-compactor, also called mask data, is stored in a compressed format on the tester and decompressed on-chip. The authors applied this technique to four industrial designs and obtained 26-fold to 60-fold reduction in test response data volume with no impact on test quality.
  • Keywords
    built-in self test; integrated circuit design; integrated circuit testing; logic testing; shift registers; BIST; LFSR architecture; VLSI test; response compaction; test response bits; tolerant response; unknown logic values; Circuit faults; Circuit simulation; Circuit testing; Clocks; Compaction; Computer architecture; Integrated circuit reliability; Integrated circuit testing; Logic design; Logic testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2005. Proceedings. 42nd
  • Print_ISBN
    1-59593-058-2
  • Type

    conf

  • DOI
    10.1109/DAC.2005.193784
  • Filename
    1510303