Title :
A BIST methodology for comprehensive testing of RAM with reduced heat dissipation
Author :
Cheung, Hugo ; Gupta, Sandeep K.
Author_Institution :
Rockwell Int. Corp., Newport Beach, CA, USA
Abstract :
The severity of excessive heat dissipation during concurrent BIST of memory modules has been documented previously (1993). In this paper, the authors present new versions of several memory tests that reduce heat dissipation during testing. Each proposed test has the same fault coverage and time complexity as the original version but it reduces heat dissipation by a factor of two or more. For three of the tests, the heat dissipation is reduced by factors of four to sixteen. The design of BIST circuitry required to implement the proposed tests are presented and it is shown that additional area overhead incurred is very small
Keywords :
CMOS memory circuits; SRAM chips; cooling; design for testability; heat sinks; integrated circuit testing; integrated memory circuits; random-access storage; BIST; BIST circuitry; CMOS SRAM; RAM; area overhead; comprehensive testing; heat dissipation; memory modules; memory tests; time complexity; Application specific integrated circuits; Built-in self-test; Circuit faults; Circuit testing; Costs; Hardware; Logic testing; Packaging; Random access memory; System testing;
Conference_Titel :
Test Conference, 1996. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-3541-4
DOI :
10.1109/TEST.1996.557026
