Title :
DFT strategy for Intel microprocessors
Author :
Needham, W. ; Gollakota, Naga
Author_Institution :
Intel Corp., Chandler, AZ, USA
Abstract :
This paper describes the progress in DFT techniques applied to Intel´s X86-family microprocessors. The approach described here shows a progressive approach to increasing the level of DFT with increasing size and complexity of the design. Implementation of DFT is based on the needs of a given functional block and that of the overall chip. Test generation strategy to augment the coverage provided by DFT features is highlighted
Keywords :
boundary scan testing; built-in self test; computer architecture; computer testing; design for testability; integrated circuit testing; DFT; Intel microprocessors; Pentium; X86-family microprocessors; boundary scan; complexity; size; test generation; test registers; Automatic testing; Built-in self-test; Design for testability; Design methodology; Hardware; Manufacturing; Microprocessors; Programmable logic arrays; Read only memory; Registers;
Conference_Titel :
Test Conference, 1996. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-3541-4
DOI :
10.1109/TEST.1996.557029
