• DocumentCode
    2047098
  • Title

    Partitioning-based approach to fast on-chip decap budgeting and minimization

  • Author

    Li, Hang ; Qi, Zhenyu ; Tan, Sheldon X D ; Lifeng Wu ; Cai, Yici ; Hong, Xianlong

  • Author_Institution
    Dept. of Electr. Eng., California Univ., Riverside, CA, USA
  • fYear
    2005
  • fDate
    13-17 June 2005
  • Firstpage
    170
  • Lastpage
    175
  • Abstract
    This paper proposes a fast decoupling capacitance (decap) allocation and budgeting algorithm for both early stage decap estimation and later stage decap minimization in today´s VLSI physical design. The new method is based on a sensitivity-based conjugate gradient (CG) approach. But it adopts several new techniques, which significantly improve the efficiency of the optimization process. First, the new approach applies the time-domain merged adjoint network method for fast sensitivity calculation. Second, an efficient search step scheme is proposed to replace the time-consuming line search phase in conventional conjugate gradient method for decap budget optimization. Third, instead of optimizing an entire large circuit, we partition the circuit into a number of smaller sub-circuits and optimize them separately by exploiting the locality of adding decaps. Experimental results show that the proposed algorithm achieves at least 10X speed-up over the fastest decap allocation method reported so far with similar or even better budget quality and a power grid circuit with about one million nodes can be optimized using the new method in half an hour on the latest Linux workstations.
  • Keywords
    Linux; VLSI; circuit optimisation; conjugate gradient methods; electronic engineering computing; integrated circuit design; logic partitioning; minimisation; sensitivity; time-domain analysis; workstations; Linux workstations; VLSI physical design; adjoint network method; budget quality; budgeting algorithm; conjugate gradient approach; conjugate gradient method; decap budget optimization; decap estimation; decap minimization; decoupling capacitance allocation; line search phase; on-chip decap budgeting; optimization process; partitioning approach; power grid circuit; sensitivity calculation; time-domain method; Algorithm design and analysis; Capacitance; Character generation; Circuits; Gradient methods; Minimization methods; Optimization methods; Partitioning algorithms; Time domain analysis; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2005. Proceedings. 42nd
  • Print_ISBN
    1-59593-058-2
  • Type

    conf

  • DOI
    10.1109/DAC.2005.193795
  • Filename
    1510314