DocumentCode
2047276
Title
Simulation and stability analysis of 6T and 9T SRAM cell in 45 nm era
Author
Akashe, Shyam ; Tiwari, Neeraj Kumar ; Sharma, Ritu
fYear
2012
fDate
17-19 Dec. 2012
Firstpage
1
Lastpage
6
Abstract
Advancement of technology greatly affects the leakage current and leakage power of SRAM cell. Leakage current in SRAM cell is dominating factor, which is mainly affects the power consumption. This paper presents the design and evaluation of a new SRAM cell made of nine transistors (9T). The 9T SRAM cell achieves improvements in leakage current, power dissipation performance and read stability compared with 6T SRAM cell for low power operation. This paper compares the performance of two SRAM cell topologies, which includes the conventional 6T cell and 9T cell. In particular the leakage current, leakage power and static noise margin (SNM) of each cell is designed and examined. Compared to a conventional 6T SRAM cell, the proposed 9T SRAM cell reduces the power consumption by 62.45% and enhances the read stability by 43.37%.
Keywords
SRAM chips; power aware computing; transistors; 6T SRAM cell; 9T SRAM cell; SRAM cell; SRAM cell topology; leakage current; leakage power; power consumption; power dissipation performance; read stability; size 45 nm; stability analysis; static noise margin; static random access memory; transistor; SRAM; leakage current; leakage power; static noise margin (SNM);
fLanguage
English
Publisher
ieee
Conference_Titel
Power, Control and Embedded Systems (ICPCES), 2012 2nd International Conference on
Conference_Location
Allahabad
Print_ISBN
978-1-4673-1047-5
Type
conf
DOI
10.1109/ICPCES.2012.6508061
Filename
6508061
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