Parallel delay fault coverage and test quality evaluation

An efficient fault simulation based evaluation methodology for the determination of fault coverages and test set quality is a practical way to obtain a set of high quality gate delay fault detecting tests. Unfortunately, the methodology is computationally intensive enough to be intractable for reasonably large VLSI circuits. An attractive alternative for speeding up these computation algorithms is parallel processing. In this paper, we present, for the first time, parallel algorithms for gate delay fault simulation and fault coverage determination through test quality evaluation. These algorithms are theoretically analyzed, and experimental studies of their implementation are reported. Studies of load balancing schemes for these algorithms are also presented. The results conform to the theoretically predicted performance, with speedups of up to 12 being obtained for 15 processors