A new architecture for the generation of picture based CAPTCHA: Double binary convolutional turbo decoder using low power memory reduced traceback MAP decoding

Low power has emerged as a principal theme in today´s electronics industry. The need for low power has caused a major paradigm shift where power dissipation has become as important a consideration as performance and area. This project aims at reducing the power consumption of the decoder by proposing a low-power memory-reduced traceback Maximum A Posteriori (MAP) Algorithm decoding. Instead of storing all state metrics, the traceback MAP decoding reduces the size of the SMC by accessing difference metrics. The proposed traceback computation requires no complicated reversion checker, path selection, and reversion flag cache. Two pairs of the traceback computation are introduced for the radix-4 double-binary (DB) MAP decoding. For double-binary MAP decoding, radix-2 × 2 and radix-4 traceback structures are introduced to provide a tradeoff between power consumption and area. The traceback radix-2 × 2 pair has low hardware costs and the radix-4 traceback pair has short path delays.